State machines are often used by designers to implement sequential logic function to control the behavior of a machine, circuit, or system. With a state machine, the designer may control all state outputs and transitions for any given input. In the past, state machines were implemented in hardware using logic gates, manually specified with via a schematic. A disadvantage of such state machines is that once a design has been implemented, changing the control functions of the state machine requires redesigning the hardware circuit thereby making any changes difficult or impractical to effect. Consequently, state machines are increasingly being implemented in hardware description languages such as VHDL or Verilog. One advantage of implementing state machines in software is that doing so provides flexibility to modify or alter the control functions of the state machine since a designer or programmer may modify and recompile the source code to implement desired changes.
Because of performance and design considerations, it may be desirable to pass from one state to another within a state machine without occupying an extra clock cycle by combining the two states based on a signal outside the machine. Since state transitions outside of a clock boundary are impossible to implement in a synchronous environment, the designer must combine the logic from one state into a second state. A “flag” signal is then used to select the logic or decisions of the first state while the state machine is actually in second state. In this manner, the state machine need not actually enter the first state and can remain synchronous. However, using this method, RTL code for both states must be duplicated in each state. When RTL code is duplicated in this manner, subtle errors in the code can occur if all copies of the code are not updated together. Moreover, as the RTL code of the state machine is written, portions of the code may be duplicated incorrectly due to human error. Consequently, it would be desirable to provide a method for combining states of a state machine without maintaining duplicate copies of the same RTL code.